Electronics & Communications Engineering

Aravalli Sainath Chaithanya

Assistant Professor
Education
: M. Tech.
Email
: chaithanya@rgukt.ac.in
Phone
: +91 - 8520948605
Work Experience
  1. Working as an Assistant Professor, Rajiv Gandhi University of Knowledge Technologies(RGUKT) Basar from September 2016 - till date
  2. Worked as an Trainee engineer, at UTL Technologies, Bangalore from June 2016 - September 2016
  3. Worked as a intern in Centre for Intelligent Machines and Robotics (CIMAR) , BHEL R&D – Bal Nagar from November 2014 - may 2015
Publications
International Journals
  1. Deepak Sachan , A Sainath Chaithanya “Image Processing Technique for Drilled Holes Inspection in Large Rectangular Plate”; Int. Journal of Engineering Research and Application www.ijera.com ISSN : 2248-9622, Vol. 8, Issue3, ( Part -1) march2018, pp.21-27
Projects
Projects handled at UTL technologies:
  1. Title: Developed tape out for Wallace tree multiplier using Cadence encounter tool
    Tools: Cadence NC-Sim, Encounter (rtl2gdsii.);
  2. Title: Worked in developing functional environment for FIFO using system Verilog
    Tools: Model sim10.0 Platform: System Verilog
  3. Title: Worked in developing verification environment for Router using UVM
    Tools: Model sim10.0 Platform: UVM, System Verilog
Master’s Thesis:Image processing technique for drilled hole inspection in large rectangular plate

Additional M’tech projects:
  1. Design of 8 bit SAR ADC in VERILOG HDL.
  2. Designing layout for MU0 1bit ALU Logic in Cadence.
Projects Supervision(18)
  1. Design and Implementation of Embedded Vision System using Zed board FPGA
  2. VLSI Implementation of Artificial Neural Network.
  3. Data Transactions from UART to SPI Slave Devices
  4. Designing of NOC using Five Port Router
  5. Design of DDR SDRAM controller
  6. Designing Communication Bridge between AMBA APB to UART
  7. Design of Low Power and High Performance Flip-Flops, logic gates by adiabetic logic techniques
  8. Design of 8 bit RISC processor using Verilog HDL
  9. Design and Interfacing of I2C Master with Register and LCD Slaves
  10. Design of AMBA AXI4-Lite for Effective Read/Write Transactions with a Customized Memory etc
Research Interests
  • VLSI-Front end logical design, Backend-physical design and verification methodologies
  • Advanced Micro controllers
  • Bus protocols, architectures
  • System on chip designs
  • Image processing & Machine Learning
Subjects Taught
B.Tech
  • Digital System Design (E3-ECE)
  • VLSI engineering (E3-ECE)
  • Signals and systems (E3-CSE)
  • Micro controller interfacing Lab(E4-ECE, EEE)
  • VLSI Simulation Lab (E3-ECE)
Workshops/Short Term Courses/Webinars
  • Three day FDP on "Designing with ZYNQ Soc and its applications" held at JNTU-Hyderabad oct’19 by CoreEL Technologies
  • Attended “MATLAB EXPO 2019 INDIA” a 1 day seminar on Matlab and its innovations organized by Capricot Technologies. On Feb ’19.
  • Webinar on Block Level Design Using IP Integrator in Xilinx Vivado in association with CoreEL Technologies and Xilinx
  • Webinar on Physical Design and Challenges in VLSI:: CoreEL Technologies on june’20
Additional Responibilites & Academic Achievements
Department Level Faculty in-charge/coordinator
  • Project Coordinator, 2018-19, Department of ECE, RGUKT, Basar.
  • Seminar Coordinator, 2016-17, Department of ECE, RGUKT, Basar.
  • Tech Fest event coordinator - Extronics2K18
  • Micro controller interfacing Lab (2017-Till Date), Department of ECE, RGUKT, Basar.
  • VLSI Simulation Lab (2016-Till Date), Department of ECE, RGUKT, Basar.
  • Academic Planning Committee (APC) Adversary Member in dept of ECE
Academic Achievements
  • Qualified in GATE-2013,16,17,19
  • Qualified for Assistant Professor in JUNE 2019 and DECEMBER 2019 NTA-UGC NET
  • Grabbed Best project Awards and Paper awards in UG/PG
Youtube channel: https://www.youtube.com/channel/UCuxecd6IXesoLhXMlLeDS0Q