Faculty Profile

Dr. CHINTAM SHRAVAN

ASSISTANT PROFESSOR

Electronics and Communications Engineering

Degree	Programme / Specialization	University / Board
UG	B.Tech	JNTUH
PG	M.Tech	Kakatiya University
Ph.D	Doctor of Philosophy in Electronics and Communication Engineering	Osmania University

Institution / Organization	Designation	From	To
Matrusri Engineering College	Assistant Professor	2015	2016
RGUKT BASAR	Assistant Professor	2016	2025

1. Ch. Shravan, S. K. Marri, R. Saidulu, P. Tejasvey, and S. R. Krishan G, 'A Novel High Computing Power Efficient VLSI Architectures of Three Operand Binary Adders’, International Journal of Engineering and Advanced Technology, vol. 12, no. 5. Blue Eyes Intelligence Engineering and Sciences Engineering and Sciences Publication - BEIESP, pp. 61–71, Jun. 30, 2023. doi: 10.35940/ijeat.e4188.0612523. (SCI/Scopus- H Index-32, Q4) (Impact Factor-0.322)
2. Kasturi Akash, Chintam Shravan, A Nagajyothi, "Storage node and Power analysis of 5-Transistor GC-eDRAM for longer Retention time", International Journal of Emerging Technologies and Innovative Research, ISSN:2349-5162, Vol.10, Issue 5, page no.e369-e378, May-2023, doi: http://doi.one/10.1729/Journal.34182.
3. Shravan, C., Fatima, K. & Sekhar, P.C. (2024). “Design and Develop Low-Power Memory Controller for Gain Cell−Embedded Dynamic Random-Access Memory cell using intelligent clock gating”, Telecommunication and Radio Engineering, Volume 83, Issue 8, pp. 83-94, DOI: 10.1615/TelecomRadEng.2024049973. (SCI/Scopus H Index-25, Q4) (Impact Factor 0.234)
4. Chintam Shravan, Samuel Singaram, Rajesh Dhanavath, Meesala Babitha, and Konda Srujana, “Enhancing Biometric Authentication Security through ECG Signals” POSITIF Journal, ISSN:0048-4911, Vol.24, Issue 12 page no. 111-117, Dec-2024, DOI.org/10.37896/psj31.12/21911 (SCI/Scopus H Index-5, Q4) (Impact Factor-0.1)
5. Shravan, C., Fatima, K. & Sekhar, P.C. “Design and Development of Novel Refresh Technique for Gain Cell Embedded DRAM”. SN COMPUT. SCI. 4, 786 (2023). https://doi.org/10.1007/s42979-023-02223-z (SCI/Scopus H Index-49, Q2) (Impact Factor-1.137)
6. Shravan, C., Fatima, K., & Sekhar, P. C. (2023). “Design and Develop Efficient Arbitration Technique to Handle the Multiple Refresh Requests in Multi-Processor SoC”. International Journal on Recent and Innovation Trends in Computing and Communication, 11(8s), 341–350. https://doi.org/10.17762/ijritcc.v11i8s.7214 (SCI/Scopus H Index-15, Q4)(Impact Factor 0.807)

1. Shravan, CH.; Pavan Kumar, CH.; Sivani, K., "A novel approach for power reduction in asynchronous circuits by using AFPT," Wireless and Optical Communications Networks (WOCN), 2014 Eleventh IEEE International Conference on , vol., no., pp.1,7, 11-13 Sept. 2014, doi: 10.1109/WOCN.2014.6923091
2. Shravan, Ch.; Pavan Kumar Ch.; Sivani, K., "A novel approach for power-gating technique with Improved Efficient Charge Recovery Logic," Smart Electric Grid (ISEG), 2014 IEEE International Conference on , vol., no., pp.1,8, 19-20 Sept. 2014 doi: 10.1109/ISEG.2014.7005583.
3. O. Anjaneyulu, CH. Shravan, A. Veena, C. V. Reddy, “Self Driven Pass Transistor based Low Power Pulse Triggered Flip-Flop Design (LPPF)” IEEE International Conference on Signal Processing and Communication Engineering Systems (SPACES), 2nd & 3rd January, 2015, KL University, Vijayawada, Andhra Pradesh, India. Doi: 10.1109/SPACES.2015.7058266
4. C. Shravan, S. K. Marri and T. Kampasati, "VLSI Architectures of Three Operand Binary Adders," 2023 IEEE International Conference on Advances in Electronics, Communication, Computing and Intelligent Information Systems (ICAECIS), Bangalore, India, 2023, pp. 338-343, doi: 10.1109/ICAECIS58353.2023.10170061.

1. Life Member in ISTE (LM 142896)
2. Member in IEEE (99010182)
3. MIAENG (345713)

1. One-Day workshop on “National Programme on technology Enhanced learning (NPTEL)” organized by IIT Madras on 9th July, 2016 at Vardhman College of Engineering, Hyderabad.
2. Short-term practical training and evaluations for “Instructional Excellence in Intelligent Systems under the Intel College Excellence Program” conducted by Rajiv Gandhi University of Knowledge technologies, Basar, From 13th -16th Sept, 2016.
3. One-week faculty development program on “Real Time Embedded Systems and IoT, Its Applications” Organized by the E & ICT Academy, National Institute of Technology, Warangal, at the Department of ECE, Vardhman College of Engineering (Autonomous), Hyderabad from 5th -10th December, 2016. (Sponsored by Meity, Govt of India)
4. Short-term course on “ENGINEERING RESEARCH METHODOLOGY (ERM-2017)” held during 11-14 December, 2017 in the department of Mechanical Engineering, University College Engineering (Autonomous), Osmania University, Hyderabad, Telangana state-500007
5. One-week GIAN (Global Initiative of Academic Networks) course on “ADVANCED CMOS CLOCK GENERATION CIRCUITS” (Course Code:171036D01) organized by the Department of Electronics and Communication Engineering National Institute of Technology Warangal during December 25 – 29, 2017. Foreign Faculty/Expert: Dr. Pavan Kumar Hanumolu.
6. TEQIP-III sponsored Five Day Continuing Education Program on “5G TECHNOLOGIES” organized by the Department of Electronics and Communication Engineering, National Institute of Technology, Warangal from 14th to 18th May 2018
7. One-week faculty development program on “FUTURE NANO ELECTRONIC DEVICES & CIRCUITS” organized by Department of Electronics & Communication Engineering, MGIT, Hyderabad from 6th to 10th July 2020.
8. Two-week online faculty development programme on “System Design Methodologies for Embedded, IoT, AI, & HPC using Intel FPGA” jointly organized by Electronics and ICT academics held from 19th to 30th April 2021 under the “Scheme of financial assistance for setting up of Electronics and ICT Academies” of the Ministry of Electronics and Information Technology (MeitY), Government of India.
9. The AICTE-ISTE approved Orientation/Refresher Programme on "Advanced VLSI Design Using Microwind" conducted from 06.05.2021 to 12.05.2021, organized by Dr. Rajendra Gode Institute of Technology & Research, Amravati, Maharashtra
10. One week workshop on "VLSI to System Design: Silicon to End Application Approach" conducted by AICTE, ARM Education and ST Micro-electronics from 31st July 2024 to 4th August 2023.
11. 40-hour Faculty Development Programme on “Role of Artificial Intelligence for Computer Vision and Medical Imaging Applications” conducted from 4th to 12th March 2024, organised by E&ICT Academy, NIT Warangal and Muffakham Jah College of Engineering and Technology, Hyderabad, sponsored by MeitY, Government of India.
12. AICTE-recognised One Week Faculty Development Programme on "AI for Engineering Applications" conducted by NITTTR, Chandigarh, hosted Electronics and Communication Engineering Department at Rajiv Gandhi University of Knowledge Technologies, Basar, Telangana, from 4th November 2024 to 8th November 2024.

1. ESIOT (E4-EC4403)
2. Analog Electronic Circuits (E2-EC2201)
3. RFMW (E3-EC3102)
4. Digital Electronic Circuits (E2-EC2202 & E1-EC1101)
5. Linear Control System Engineering (E2-EC2202)
6. Electrical and Electronic Measurement & Instrumentation (E4-EC4426)
7. Digital Communication (E3-EC3201)
8. Basic Electrical Engineering (E1-EE1002 & E1-EE1203)
9. Signals & Systems (E2-EC2103)
10. Mixed Signal Circuit Design (MSCD)
11. Network Analysis (E1-EC1202)
12. Computer Architecture (E3-EC3102)

1. Current based Data Retention Time (IDRT) characterization methodology for Gain-Cell Embedded DRAM, as an alternative of existing SRAM Memory cell
2. Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection.
3. A 3-Transistor nMOS-only logic compatible Gain-Cell Embedded DRAM for alternative SRAM’s at 1000 mV in 45-nm FD-SOI.
4. Improved Gain-Cell Embedded DRAM: Timing; Availability, bandwidth and area improvement.
5. Efficient VLSI Implementation of a Sequential Finite Field Multiplier Using Reordered Normal Basis in Domino Logic.
6. Study on the Anti-Theft Technology of Museum Cultural Relics based on Internet of Things (IoT).
7. A Novel High Computing Power Efficient VLSI Architectures of Three Operand Binary Adders
8. Enhancing Biometric Authentication Security through ECG Signals
9. CMOS Based Architecture for HIGH SPEED BCD ADDITION

1. Member, NAAC Committee (17-12-2019 to 2021), RGUKT, Basar
2. Member, Cultural Committee (07-02-2018 to 30-07-2018 ), RGUKT, Basar
3. Cultural Coordinator (2017-2018), Department of ECE, RGUKT, Basar.
4. Library Coordinator (2018 - Feb 2021), Department of ECE, RGUKT, Basar
5. NAAC Coordinator (2017-2021), Department of ECE, RGUKT, Basar
6. Mini-Project and Comprehensive Viva Co-ordinator, Department of ECE, AY 2023-24, RGUKT-Basar
7. Tech-Fest Co-ordinator (2025), Department of ECE, RGUKT-Basar.
8. Library Co-ordinator (AY 2024- Till date), Department of ECE, RGUKT-Basar.