Faculty Profile

Dr. ARAVALLI SAINATH CHAITHANYA

ASSISTANT PROFESSOR

Electronics and Communications Engineering

1. VLSI-Front end logical design, Backend-physical design and verification methodologies 2. Advanced Micro controllers 3. Bus protocols, architectures 4. System on chip designs 5. Image processing & Machine Learning

Degree	Programme / Specialization	University / Board
PG	M.Tech-VLSI System Design	JNTU Hyderabad
UG	B.Tech-ECE	JNTU Hyderabad

Institution / Organization	Designation	From	To
RGUKT-Basar	Asst. Professor	2016	till date

1. Deepak Sachan, A Sainath Chaithanya “Image Processing Technique for Drilled Holes Inspection in Large Rectangular Plate”; Int. Journal of Engineering Research and Application www.ijera.com ISSN: 2248-9622, Vol. 8, Issue3, ( Part -1) March 2018, pp.21-27

1. Qualified in GATE-2016,17, 19, 20
2. Qualified for Assistant Professor in JUNE 2019 and DECEMBER 2019 NTA-UGC NET
3. Grabbed Best project Awards and Paper awards in UG/PG

1. Three-day FDP on "Designing with ZYNQ Soc and its applications" held at JNTU-Hyderabad oct’19 by CoreEL Technologies
2. Attended “MATLAB EXPO 2019 INDIA” a one-day seminar on Matlab and its innovations organized by Capricot Technologies. On Feb ’19.
3. Attended Webinar on Block Level Design Using IP Integrator in Xilinx Vivado in association with CoreEL Technologies and Xilinx
4. Attended Webinar on Physical Design and Challenges in VLSI:: CoreEL Technologies on June’20
5. Medical Image processing and 3D Applications
6. Medical Image Processing & its applications in Automated Disease Detection
7. 5G and Emerging Technologies

1. Computer Vision (E4-ECE)
2. Wireless Communications (E4-ECE)
3. Digital System Design (E3-ECE)
4. VLSI engineering (E3-ECE)
5. Signals and systems (E3-CSE)
6. PTSP(E2-ECE)
7. Microcontroller interfacing Lab(E4-ECE, EE)
8. DSD/VLSI Simulation Lab (E3-ECE)
9. AEC, DEC Labs (E2-ECE,CSE,EE)

1. B.Tech - 24 projects till date

1. Academic Planning Committee (APC) Adversary Member in dept of ECE, 2021-22